The present invention relates to bias generator circuits, and in particular to bias generator circuits for 3.3 volt or lower applications.
In order to reduce power consumption and improve clock speed, there has been a growing trend in semiconductor technology (including microprocessors, memories, and complex programmable logic devices, etc.) to design devices that have core circuitry operating at a lower power supply voltage. These circuits still must be able to interface with other circuitry which runs at higher voltage levels. For example, the core circuitry for a microprocessor may operate with a 3.3 volt or 2.9 volt voltage supply but must be able to receive signals swinging between ground and 5 volts. In newer technologies, a 1.9 volt supply for the core circuitry may be used, with an interface to the 3.3 volt external bus.
One problem that arises is that certain transistors for the interface must be provided with a 3.3 volt supply or other supplies above the 1.9 volt level. However, the transistors are limited to having a maximum of approximately 1.9 volts across them. Accordingly, there is a need for bias generator circuits at different levels to limit the excursions of the voltage of particular nodes, or to provide particular desired voltage levels using transistors that themselves do not exceed 1.9 volts (or whatever other core voltage level is used).